In a memory circuit, it is often desirable to use clock lines whose maximum voltage is greater than the supply voltage V.sub.cc. Typically, these clock lines are loaded by large capacitances which make it difficult for them to be driven above V.sub.cc. The prior art shows the use of a bootstrap capacitance which is always fully charged and discharged as the load capacitance is. In these circuits, the bootstrap capacitance is tied directly to the load capacitance.